A storage system generally comprises a controller and a randomly accessible nonvolatile recording medium. This recording medium, for example, is a disk array comprising a plurality of hard disk drives (HDD) or nonvolatile solid state drives (SSD). The controller, for example, comprises a front-end interface (hereinafter “FEIF”) for connecting to a higher-level device (a host system or the like), a back-end interface (hereinafter “BEIF”) for connecting to the disk array, and a cache memory (hereinafter “CM”) for temporarily storing data that the higher-level device writes/reads to/from the disk array. In addition, the controller comprises a processor for controlling the transfer of data between the higher-level device and the CM, and between the disk array and the CM. “PCI Express” is known as a communication network standard for connecting the processor, FEIF and BEIF. Also, a “Multi-Root I/O Virtualization and Sharing Specification” (hereinafter “MR-IOV”), which is a standard for a plurality of processors to share an I/O device, is known as a PCI Express expansion standard. For example, Patent Literature 1 discloses technology related to a communication network in a case that applies MR-IOV.
In MR-IOV, for example, the communication network is configured from a plurality of root complexes (hereinafter “RC”) to which processors are connected, a plurality of root ports (hereinafter “RP”) included in the RC, a plurality of endpoints (hereinafter “EP”), which are the base points of data input/output, and a plurality of switches for connecting the RP and the EP. Then, the respective EPs are configured so as to enable the provision (so as to enable the processor to control the transfer of data over these EPs) of a function (a data transfer function that transfers inputted data to another device) to each processor that accesses the EP via the RP. In accordance with a configuration like this, a plurality of processors are able to share the respective EPs, and are each able to independently access the EP via the RP (are each able to independently control the transfer of data over the EP). In accordance with this, it is possible for a plurality of processors to independently carry out data transfer operations without increasing the number of EPs, thereby enhancing data transfer processing performance.
Focusing on one RP in the MR-IOV, a tree topology configured from this RP and the EPs and switches logically connected to this RP is called a “virtual hierarchy” (hereinafter “VH”). In a communication network that conforms to the MR-IOV (hereinafter “MR-IOV network”), the same number of VHs as the plurality of RPs exists inside this MR-IOV network. One VH represents the data transfer address space controlled for each RP by a single processor.
For example, it is supposed that a first VH configured from a RP1, a EP1 and a EP2, and a second VH configured from a RP2, the EP1 and the EP2 exist inside the MR-IOV network. Then, it is supposed that the RP1 is disposed in a RC1, to which a processor 1 is connected, and that the RP2 is disposed in a RC2, to which a processor 2 is connected. In accordance with this, the processor 1 is able to independently control a data transfer from the EP1 to the EP2 (or vice versa) by way of the RP1 on the first VH, and the processor 2 is able to independently control a data transfer from the EP1 to the EP2 (or vice versa) by way of the RP2 on the second VH.